The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures created from a process that integrates the formation of a vertical electrostatic discharge protection device with that of a planar fin field effect transistors (finFET).
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as fin field effect transistors (finFETs), are fabricated in and on a single wafer. FinFETs employ semiconductor fins to introduce on-wafer topography. The semiconductor fins are often formed as an array of semiconductor fins having a periodicity, or fin pitch, to minimize etch bias due to pattern factor, i.e., the fraction of the area of the semiconductor fins within a unit area. An example of the finFET is a planar finFET. Such a device can include a gate region formed over fins. A source and drain is formed by connecting to the fins on opposing sides of the gate.
Technology scaling unfavorably affects the electrostatic discharge (ESD) protection of integrated circuits by reducing FET oxide and junction breakdown voltage, and diode current shunting capability as well as by increasing the interconnect resistivity. Further, the I/O data-rate increasingly limits the capacitive budget, exacerbating the shrinkage of ESD design space. As such, it is important to find ESD solutions that minimize parasitic loading while achieving superior robustness.